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RT9245A
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
RT9245A is a multi-phase buck DC/DC controller integrated with all control functions for AMD K8 CPU or Intel (R) GHz CPU which is VRD10.x-compliant. The RT9245A could be operated with 2, 3 or 4 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9245A implements both voltage and current loops to achieve good regulation, response and power stage thermal balance. RT9245A applies the DCR sensing technology newly. The RT9245A extracts the DCR of output inductor as sense component to deliver a precise load line regulation and good thermal balance for next generation processor application. Current sense setting, droop tuning, VCORE initial offset and over current protection are independent on compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT9245A supports AMD K8 5-bit VID and Intel(R) VRD10.x with 6-bit VID input, precise offset value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system. The RT9245A comes to a small footprint package TSSOP-28.
Features
Multi-Phase Power Conversion with Automatic Phase Selection 6-bits VRD10.x or 5-bit K8 DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Power Stage Thermal Balance by DCR Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and SoftStart High Ripple Frequency Times Channel Number 28-TSSOP Package RoHS Compliant and 100% Lead (Pb)-Free
Applications
Intel(R) Processors Voltage Regulator : VRD10.x and AMD K8 Low Output Voltage, High Current DC-DC Converters Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
VID4 VID3 VID2 VID1 VID0 VID125/VIDSEL SGND FB COMP PGOOD DVD SS RT VOSS 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PWM1 PWM2 PWM3 PWM4 CSP4 CSP2 CSP3 CSP1 GND ADJ IOUT CSN IMAX
Ordering Information
RT9245A Package Type C : TSSOP-28 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
TSSOP-28 Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. www.richtek.com 1
DS9245A-05 March 2007
ATX 12V
+
1uH C11 1000uF C12 4.7uF C14 1000uF
+ +
VIN
ATX 12V
C10 1uF C13 R22 0 Q1 L1 0.3uH IPD09N03LA Q2 IPD06N03LA C16 3.3nF R23 2.2 4.7uF C15 1000uF R21 D1 10 1N4148 1 4 VCC PHASE LGATE PGND 6 5 7 RT9619 8 UGATE BOOT
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VCC 5V
2 3 NC R10 10 PWM C9 1uF
RT9245A
RT9245A
+ +
C4 1uF 28 27 1 4 VCC PHASE LGATE PGND 6 5 IPD06N03LA Q4 7 IPD09N03LA R26 2.2 C17 1uF R11 470 R12 470 R13 470 2 PWM 3 NC RT9619 8 UGATE BOOT R25 0 Q3 R24 10 D2 1N4148 4.7uF L2 0.3uH C19
ATX 12V
C18 1uF
VIN
C21 C20 1000uF 1000uF
Typical Application Circuit
VID125
6 VID125
VCC PWM1 PWM2 26 PWM3 PWM4 CSP4 CSP2 CSP3 21 CSP1
19 R15 33 R16 1 4 C23 1uF 2 3 PWM NC R28 10 D3 1N4148 VCC C8 1uF R14 470 C24 1uF 20 C7 1uF 22 23 24 25
/VIDSEL
VOUT
VID4
VID3
1 VID4 2
VID2
3
VID3
C35 to C44 560uF x 10 +
VID2
VID1
VID0
4 VID1 5
VID0
+
C22 3.3nF NTC 10k C47 to C64 10uF x 18
R1 0
7
SGND
680pF
8
FB ATX 12V
C5 1uF C6 1uF
C1 5.6pF
9
R2 1.5k
COMP GND ADJ 18 IOUT CSN IMAX
R19 6.8k 15 R18 100k D5 R20 BAT254 100 16 R17 470 17
VIN
R27 240 C27 C26 1000uF 1000uF
+ +
Figure A. For Intel
RT9619 8 UGATE BOOT PHASE LGATE PGND 6 7 5 R29 0 Q5 IPD09N03LA Q6 IPD06N03LA
R3 15k
C2 2.7nF
10
VC C 3.3V ATX 12V
R5 10k
R4 10k
PGOOD
C25 4.7uF
11
DVD
R6 1.2k
C3 12 SS 68nF R7 20k 13
L3 0.3uH R30 2.2 C28 3.3nF
RT
R8 100k 14
VOSS
VCC 5V
R9
ATX 12V
C30 1uF
VIN
C33 C32 1000uF 1000uF
+ +
C31 R31 10 D4 1N4148 1 4 C29 1uF 2 3 PWM NC RT9619 8 UGATE BOOT VCC PHASE LGATE PGND 6 7 5 R32 0 Q7 IPD09N03LA Q8 IPD06N03LA R33 2.2 C34 3.3nF 4.7uF
DS9245A-05 March 2007
L4 0.3uH
ATX 12V
1uH
VIN
+
C11 1000uF C12 4.7uF C14 1000uF
+ +
ATX 12V
C10 1uF C13 R20 10 D1 1N4148 R21 0 Q1 L1 1uH IPD09N03LA Q2 IPD06N03LA C16 3.3nF R22 2.2 RT9619 8 1 BOOT UGATE 4 VCC 7 PHASE 2 3 NC PGND 6 R9 10 R38 820 C4 1uF
+ +
4.7uF
C15 1000uF
DS9245A-05 March 2007
VCC 5V
PWM LGATE 5 C9 1uF
RT9245A VCC PWM1 PWM2 PWM3 PWM4 24 CSP4 CSP2 CSP3 CSP1 GND ADJ IOUT
1 4 C23 1uF 2 3 PWM NC 17 16 R16 470 R17 100k R18 6.8k D5 R19 BAT254 100 R15 C8 1uF R27 10 D3 1N4148 VCC 18 R14 33 19 C24 1uF 20 C7 1uF R13 1k 21 C6 1uF R12 1k 22 C5 1uF R11 1k PGND 6 23 R10 1k LGATE 5 IPD06N03LA Q4 2 PWM 3 NC C17 1uF PHASE 25 4 VCC 7 IPD09N03LA R25 2.2 26 1 RT9619 8 BOOT UGATE 27 R24 0 Q3 R23 10 D2 1N4148 4.7uF L2 1uH 28 C19
ATX 12V
C18 1uF
VIN
C21 C20 1000uF 1000uF
6 VID125
/VIDSEL
VOUT
VID4
VID3
1 VID4 2
VID2
3
VID3
C35 to C46 1000uF x 12 +
VID1
4
VID0
5
VID2 VID1
VID0
+
C22 3.3nF C47 to C50 10uF x 4 NTC 10k
R1 0
7
SGND
C51
NC
8
FB ATX 12V
C1
33pF
9
R2 3k
COMP
VIN
R26 240 C26 C27 1000uF 1000uF
+ +
Figure B. For AMD
RT9619 8 BOOT UGATE PHASE 7 5 LGATE PGND 6 R28 0 Q5 IPD09N03LA Q6 IPD06N03LA
C2 10nF
R3 15k VCC 3.3V/FSBVTT
10
C25 4.7uF
ATX 12V
R5 10k
R4 10k
PGOOD
11
DVD CSN IMAX
15
C3 68nF
12
SS
L3 1uH
R6 1.2k
13
R7 20k 14
RT
VOSS
R8 100k
R29 2.2 C28 3.3nF
ATX 12V
C30 1uF
VIN
C32 C33 1000uF 1000uF
+ +
C31 R30 10 D4 1N4148 R31 0 1 4 C29 1uF 2 3 PWM NC RT9619 8 BOOT UGATE VCC PHASE 7 5 LGATE PGND 6 Q7 IPD09N03LA Q8 IPD06N03LA R32 2.2 C34 3.3nF 4.7uF
RT9245A
L4 1uH
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RT9245A
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4), VID0 (Pin 5) DAC voltage identification inputs for VRD10.x. These pins are internally pulled to 1.2V (VRD10.x) or 2.1V (K8) if left open. VID125/VIDSEL (Pin 6) When this pin pull low or left pen -->VR10 VID input, pull high to 5V -->K8. SGND (Pin 7) VCORE differential sense negative input. FB (Pin 8) Inverting input of the internal error amplifier. COMP (Pin 9) Output of the error amplifier and input of the PWM comparator. PGOOD (Pin 10) Power good open-drain output. DVD (Pin 11) Programmable power UVLO detection input. Trip threshold = 1.0V at VDVD rising. SS (Pin 12) Connect this SS pin to GND with a capacitor to set the soft-start time interval. RT (Pin 13) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. VOSS (Pin 14) VCORE initial value offset. Connect this pin to GND with a resistor to set the negative offset value. Connect this pin to VCC to set positive offset value. PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) & PWM4 (Pin 24) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 3 channels, connect PWM4 high. Two channel systems connect PWM3 high. VCC (Pin 28) IC power supply. Connect this pin to a 5V supply. CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4 (Pin 23) Current sense positive inputs for individual converter channel current sense. GND (Pin 19) Ground for the IC. IMAX (Pin 15) Programmable over currert setting. CSN (Pin 16) Current sense negative input of all channels. IOUT (Pin 17) Output Current Indication Pin. The current through IOUT pin is proportional to the output current. ADJ (Pin 18) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop.
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DS9245A-05 March 2007
DAC
PWMCP
INH
OCP Setting Power On Reset + + +
INH
Function Block Diagram
VID4 VID3 VID2 VID1 VID0 VID125 ++ OVP Trip Point ++ + + + PWMCP
INH
Oscillator & Sawtooth PWM Logic & Driver
DAC + Droop + + +
PG Trip Point
Current Correction MUX +
GAP Amplifier
SS Control + -
SUM/M
VOSS FB COMP SS
ADJ
IOUT
GND
-
-
+
Offset Currrent Source/Sink +
-
Error Amplifier
MUX
-
+
+
+
-
-
+
DS9245A-05 March 2007
IMAX PGOOD VCC DVD RT
INH
PWM Logic & Driver
PWM1
PWM2
PWM Logic & Driver
PWM3
PWMCP
INH
PWM Logic & Driver PWMCP Phase Control
PWM4
CSP1 CSP2 CSP3 CSP4
CSA
CSN
RT9245A
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RT9245A
Table 1. Output Voltage Program (VRD 10.x)
Pin Name VID4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 VID1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 VID0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 VID125 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal Output Voltage DACOUT No CPU 0.8375V 0.850V 0.8625V 0.875V 0.8875V 0.900V 0.9125V 0.925V 0.9375V 0.950V 0.9625V 0.975V 0.9875V 1.000V 1.0125V 1.025V 1.0375V 1.050V 1.0625V 1.075V 1.0875V 1.100V 1.1125V 1.125V 1.1375V 1.150V 1.1625V 1.175V 1.1875V 1.200V 1.2125V
To be continued
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RT9245A
Table 1. Output Voltage Program (VRD 10.x)
Pin Name VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID125 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal Output Voltage DACOUT 1.225V 1.2375V 1.250V 1.2625V 1.275V 1.2875V 1.300V 1.3125V 1.325V 1.3375V 1.350V 1.3625V 1.375V 1.3875V 1.400V 1.4125V 1.425V 1.4375V 1.450V 1.4625V 1.475V 1.4875V 1.500V 1.5125V 1.525V 1.5375V 1.550V 1.5625V 1.575V 1.5875V 1.600V
Note: (1) 0 : Connected to GND (2) 1 : Open (3) X : Don't Care DS9245A-05 March 2007 www.richtek.com 7
RT9245A
Table 2. Output Voltage Program (K8)
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal Output Voltage DACOUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.200 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown
Note: (1) 0 : Connected to GND (2) 1 : Open
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DS9245A-05 March 2007
RT9245A
Absolute Maximum Ratings
(Note 1) 7V GND - 0.3V to VCC + 0.3V 100C/W 150C 260C -65C to 150C 2kV 200V Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Package Thermal Resistance TSSOP-28, JA -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0C to 70C Junction Temperature Range --------------------------------------------------------------------------------- 0C to 125C
Electrical Characteristics
Parameter VCC Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis VDVD Threshold Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum Duty of Each Channel RT Pin Voltage Reference and DAC DACOUT Voltage Accuracy DAC (VID0-VID125) Input Low
(VCC = 5V, TA = 25C, unless otherwise specified)
Symbol Test Conditions Min Typ Max Units
ICC VCCRTH VCCHYS
PWM 1,2,3,4 Open
--
12 4.2 0.5 1.0 50 200 -1.9 1.0 64 1.0 -------
16 4.5 -1.06 -230 400 --70 1.1 +1 +10 0.4 0.8 ---
mA V V V mV kHz kHz V V % V % mV V V V V
VCC Rising Enable
4.0 0.2 0.94 -170 50 -0.7 58 0.9 -1 -10 --0.8 1.2
Trip (Low to High) Hysteresis
VDVDTP VDVDHYS fOSC fOSC_ADJ VOSC VRV VRT
RRT = 20k RRT = 20k
RRT = 20k VDAC 1V VDAC < 1V VRD 10.x K8 VRD 10.x K8
VDAC VILDAC VIHDAC
DAC (VID0-VID125) Input High
To be continued
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RT9245A
Parameter DAC (VID0-VID125) pull up resistor DAC Pull Up Voltage VOSS Pin Voltage Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier CSN Full Scale Source Current CSN Current for OCP Protection Over-Voltage Trip (VFB - VDAC) IMAX Voltage Power Good Output Low Voltage VPGOODL IPGOOD = 4mA --0.2 V OVT VIMAX RADJ = 0 RIMAX = 20k 320 0.9 400 1.0 450 1.1 mV V IISPFSS 100 150 ----A A GBW SR COMP = 10pF ---60 10 6 ---dB MHz V/s VVOSS VRD 10.x K8 RVOSS = 100k Symbol Test Conditions Min 2.5 --0.9 Typ 3.5 1.2 2.1 1.0 Max 4.5 --1.1 Units k V V V
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions.
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DS9245A-05 March 2007
RT9245A
Typical Operating Characteristics
Adjustable Frequency
700 600 500
PWM vs. VCOMP
70 60 50 40 30 20 10 0
RRT = 16k
400 300 200 100 0 0 10 20 30 40 50 60 70
Duty Ratio (%)
F SW (kHz)
0.5
1
1.5
2
2.5
3
3.5
RRT (kW) (k)
VCOMP (V)
Relationship Between Inductor Current and VADJ
CH1:(5V/Div) CH2:(5V/Div)
Power-Off @ IOUT = 60A
PWM
PWM
CH1:(5V/Div) CH2:(20V/Div)
VSS VADJ
UGATE
CH3:(10V/Div) CH4:(1V/Div)
LGATE IL
CH3:(50mV/Div) CH4:(20A/Div)
VCOMP Time (10s/Div)
Time (25ms/Div)
Power-On @ IOUT = 60A
CH1:(5V/Div) CH2:(5V/Div)
Ripple
VSS PWM V CORE UGATE
CH3:(20V/Div) CH4:(10V/Div) (5mV/Div)
LGATE Time (10ms/Div)
L = 0.3H, C = 5600F
Time (2.5s/Div)
DS9245A-05 March 2007
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RT9245A
DVID at Rising DVID at Falling
V CORE
(500mV/Div)
(500mV/Div)
V CORE
VID125
(2V/Div)
VID125
(2V/Div)
Time (50s/Div)
Time (50s/Div)
Transient Response
Transient Falling
(20mV/Div)
V CORE V CORE
(20mV/Div)
Time (5ms/Div)
Time (500ns/Div)
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DS9245A-05 March 2007
RT9245A
Application Information
RT9245A is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT9245A and its companion MOSFET driver RT9619 provides high quality CPU power and all protection functions to meet the requirement of modern VRM. Voltage Control RT9245A senses the CPU VCORE by SGND pin to sense the return of CPU to minimize the voltage drop on PCB trace at heavy load. OVP is sensed at FB pin. The internal high accuracy VID DAC provides the reference voltage for VRD10.x compliance. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. As conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT9245A senses the inductor current via inductor's DCR for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. If the current of some power channel is larger than average, the balancing signal reduces that channels pulse width to keep current balance. The use of single GM amplifier via time sharing technique to sense all inductor currents can reduce the offset errors and linearity variation between GMs. Thus it can greatly improve signal processing especially when dealing with such small signal as voltage drop across DCR. Droop & Load Line Setting RT9245A injects averaged current IX into the resistor RADJ connected to ADJ pin to generate a load-currentdependent voltage RADJ for droop setting :
DS9245A-05 March 2007
VADJ = 8 x IX x RADJ
VADJ is then subtracted from VID_DAC output as the real reference voltage at non-inverting input of the error amplifier as shown if Figure 1. Consequently, load line slope is calculated as : Load Line = VCORE 8 x RADJ x DCR = ICORE N x RCSN
where N is the phase number of operation.
IVOSS /4
VCORE
RCSN
EA +
DAC
VADJ
8IX RADJ
Figure 1. Load Line and Offset Function Fault Detection The chip detects FB for over voltage and power good detection. The "hiccup mode" operation of over current protection is adopted to reduce the short circuit current. The in-rush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. Phase Setting and Converter Start Up RT9245A interfaces with companion MOSFET drivers (like RT9619, RT9607 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) senses its interface voltage when IC POR acts (both VCC and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VCC. Tie the PWM to VCC and the corresponding current sense pins to GND or left float if the channel is unused. For example, for 3-Channel application, connect PWM4 high. Current Sensing Setting RT9245A senses the current flowing through inductor via its DCR for channel current balance and droop tuning.
+ -
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RT9245A
The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal circuit (see Figure 2). Figure 5 shows the time sharing technique of GM amplifier. We apply test signal at phase 4 and observe the waveforms at both pins of GM amplifier. The waveforms show time sharing mechanism and the perfomance of GM to hold both input pins equal when the shared time is on.
L VC = R x C VC = DCR x IL I X = DCR R CSN
L DCR +VCR
+ -
Time Sharing of GM
CH1:(2V/Div) CH2:(50mV/Div) CH3:(50mV/Div)
C
PWM3
RCSN
VCSP4
GMx Ix
Figure 2. Current Sense Circuit Figure 3 is the test circuit for GM. We apply test signal at GM inputs and observe its signal process output at ADJ pin. Figure 4 shows the variation of signal processing of all channels. We observe zero offsets and good linearity between phases.
CSPX ADJ + VADJ
-
VCSP4 and V CSN
V CSN
Time (1s/Div)
Figure 5 Over Current Protection RT9245A uses an external resistor R IMAX to set a programmable over current trip point. OCP comparator compares each inductor current with this reference current. RT9245A uses hiccup mode to eliminate fault detection of OCP or reduce output current when output is shorted to ground.
1 VIMAX 1 IL x DCR x x 2 RIMAX 3 RCSN
VC SUM/M MUX + GM RCSN 1k CSN
RADJ 1k
Ix
Figure 3. The Test Circuit of GM
300 250 200
GM
OCP Comparator + 1/3 IX 1/2 IIMAX
VADJ (mV)
150 100 50 0 0 25 50 75 100 125 150
VIMX
OCP Setting RIMX
VC (mV)
Figure 6. Over Current Comparator
Figure 4. The Linearity of GMx
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RT9245A
Over Current Protection
CH1:(5V/Div) CH2:(5V/Div)
PWM
For some case with preferable current ratio instead of current balance, the corresponding technique is provided. Due to different physical environment of each channel, it is necessary to slightly adjust current loading between channels. Figure 9 shows the application circuit of GM for current ratio requirement. Applying KVL along L+DCR branch and R1+C//R2 branch :
V dV dIL + DCR x IL = R1( C + C C ) + VC dt R2 dt dV R + R2 VC = R1C C + 1 dt R2 R2 For VC = DCR x IL R1 + R 2 L
VSS
Time (25ms/Div)
Figure 7. The Over Current Protection in the soft start interval
Look for its corresponding conditions :
dIL dI + DCR x IL = (R1//R2)x C x DCR x L + DCR x IL dt dt L Let = (R1//R2)x C DCR L
Over Current Protection
CH1:(5V/Div) CH2:(5V/Div)
Thus if
PWM
L = (R1//R2) x C DCR
Then VC =
R2 x DCR x IL R1+ R2
VSS
Time (25ms/Div)
With internal current balance function, this phase would share (R 1+R 2)/R 2 times current than other phases. Figure 10 & 11 show different settings for the power stages. Figure 12 shows the performance of current ratio compared with conventional current balance function in Figure 13.
IL 0.3uH 0.6m
Figure 8. Over Current Protection at steady state Current Ratio Setting
IL L DCR +VCR1 C R2
470
1uF 470
Figure 10. GM4 Setting for current ratio function
IL 0.3uH 0.6m
Figure 9. Application circuit for current ratio setting
470
1uF
Figure 11. GM1~3 Setting for current ratio function
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RT9245A
35 30 25
Current Ratio Function
IL4
Load Line without dead zone at light loads
1.31 1.3 1.29
w/o Dead Zone Compensation RCSN open
I L (A)
20 15 10 5 0 0 15 30 45 60 75
IL3 IL2 IL1
V CORE (V)
1.28 1.27 1.26 1.25 1.24 1.23
RCSN = 82k w/i Dead Zone Compensation
90
0
5
10
15
20
25
I OUT (A)
I OUT (A)
Figure 12
ILX
IL3
25 20
Figure 14
LX RX RLX CX +VX
+
30
Current Balance Function
IL4 IL1 IL2
-
VOUT
I L (A)
GMx Ix
RCSN RCSN2
15 10 5 0 0 20 40 60
Figure 15. Application circuit of GM Referring to Figure 15, IX is expressed as :
80 100
I OUT (A)
IX =
VOUT ILX_50% x RLX ILX_50% x RLX + + RCSN2 RCSN2 RCSN
(1)
Figure 13 Dead Zone Elimination RT9245A samples and holds inductor current at 50% period by time-sharing sourcing a current IX to RCSN. At light load condition when inductor current is not balance, voltage VX across the sensing capacitor would be negative. It needs a negative IX to sense the voltage. However, RT9245A CANNOT provide a negative IX and consequently cannot sense negative inductor current. This results in dead zone of load line performance as shown in Figure 14. Therefore a technique as shown in Figure 15 is required to eliminate the dead zone of load line at light load condition.
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where ILX_50% is the of inductor current at 50% period. To make sure RT9245A could sense the inductor current, right hand side of Equation (1) should always be positive: VOUT ILX_50% x RLX ILX_50% x RLX + + 0 RCSN2 RCSN2 RCSN (2)
Since RCSN2 >> RCSN in practical application, Equation (2) could be simplified as :
VOUT ILX_50% x RLX RCSN2 RCSN
Figure 14 shows that dead zone of load line at light load is eliminated by applying this technique.
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RT9245A
VID on the Fly With external pull up resistors tied to VID pins, RT9245A converters different VID codes from CPU into output voltage. Figure 16 and Figure 17 show the waveforms of VID on the fly function. Output Voltage Offset Function To meet Intel(R) requirement of initial offset of load line, RT9245A provides programmable initial offset function. External resistor RVOSS and voltage source at VOSS pin V generate offset current IVOSS = VOSS R VOSS , where VVOSS is 1V typical. One quarter of IVOSS flows through RB1 as shown in Figure 18. Error amplifier would hold the inverting pin equal to VDAC - VADJ. Thus output voltage is subtracted from VDAC - VADJ for a constant offset voltage. RFB1 VCORE = VDAC - VADJ 4 x R VOSS A positive output voltage offset is possible by connecting RVOSS to VDD instead of to GND. Please note that when RVOSS is connected to VDD, VVOSS is VDD - 2V typically and half of IVOSS flows through RFB1. VCORE is rewritten as: VCORE = VDAC - VADJ + RFB1 RVOSS
VID on the Fly (Falling)
PWM V CORE VFB
CH1:(5V/Div) CH2:(500mV/Div) CH3:(500mV/Div) CH4:(1V/Div)
VID125
VDAC = 1.500, IOUT = 5A
Time (25s/Div)
Voltage Offset Function
1.284 1.282
Figure 16
VID on the Fly (Rising)
V CORE (V)
CH3:(500mV/Div) CH4:(1V/Div) CH1:(5V/Div) CH2:(500mV/Div)
1.28 1.278 1.276 1.274 1.272 1.27 1.268 50 60 70 80 90 100 110
PWM V CORE VFB
VID125
VDAC = 1.500, IOUT = 5A
ROSS (k) (k )
Figure 19 Load Line Setting and Thermal Compensation VADJ = 8 x AVG(IX) x RADJ VOUT = VDAC - VADJ AVG(IX) is a PTC current. By properly use an NTC resistor at ADJ. Load line can be thermally compensated.
Time (25s/Div)
Figure 17
1/4 IVOSS RB1 EA + VDAC-VADJ
Figure 18. Offset Setting
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RT9245A
PGOOD Function During start-up, RT9245A will detect 5VCC and 12VIN (through DVD pin). In Figure 21, 5VCC or 12VIN is not ready during T1. V(SS) (in Figure 20) is pulled to GND by FAULT. V(EAP) is also equal to GND. V(FB) and VOUT will try to follow V(EAP) thus both V(FB) and VOUT are equal to GND during T1. During T2, both 5VCC and 12VIN are ready, FAULT = low, OPSS starts charging up CSS. In the design of RT9245A, ISS (the maximal current sink and source capability of OPSS) is limited and time-variant. During T2 (V1 = 0.4V > V(SS) > 0), ISS(T2) is equal to about 10uA. If the fault condition is OV, V(SS) and PGOOD will be pulled low immediately also. RT9245A will try to turn on low side MOSFET and turn off high side MOSFET. VOUT will fall quickly to protect CPU from high voltage. The typical waveform is shown in Figure 23.
Z2 VOUT 5VCC VDAC + OPSS N1 Z1 FB EA + EAP COMP
T2 = CSS x
V1 ISS(T2)
4x10 4 x CSS
FAULT SS CSS
After V(SS) > V1, ISS changes to about 20uA. The rising speed of V(SS) becomes about 2 times faster than in T1. In Figure 20, MOSFET N1 will turn on only if V(SS) > VTH_N1 (threshold voltage of N1) on, V(EAP) is still 0V.
0.7V = V2. Before N1 turns
Figure 20. Soft Start Circuit
5VCC_ready and DVD_ready
(V2 - V1) T3 = CSS x 1.5x10 4 x CSS ISS(T3)
After V(SS) > V2, MOSFET N1 turns on, V(EAP) starts rising. ISS(T4) is still equal to about 20uA. V(SS,EAP) is equal to VTH_N1. Due to the body effect of MOSFET N1, VTH_N1 increases with higher V(EAP). For example, if VOUT target is 1.4V, V(SS,EAP) will be equal to about 0.7V at the beginning of T4 and equal to about 1.1V at the end of T4.
PGOOD V4 V(SS)
V3 V2 V1 T1 T2 T3 T4 T5 T6
VOUT
T4 = CSS x
(V4 - V2) 9x10 4 x CSS ISS(T4)
At the end of T4, VOUT is very close to the target (within the range of 40mV). An internal 1ms timer starts. After about 1ms(T5), The open-drain output PGOOD releases. After PGOOD releases, ISS(T6) becomes about 320uA to accelerate OPSS. RT9245A enters normal operation mode and is capable to follow VID on the fly. When any of the fault conditions happens, V(SS) and PGOOD will be pulled low immediately. If the fault condition is one of 5VCC low, DVD low, OC or VID_OFF, RT9245A will try to turn off both high side MOSFET and low side MOSFET. VOUT will fall slowly to avoid negative VOUT. The typical waveform is shown in Figure 22.
Figure 21. Soft Start Waveform
PGOOD V(SS)
VOUT
5VCC_Low + DVD_Low + OC + VID_OFF
Figure 22. Waveform for 5VCC_Low, DVD_Low, OC or VID_OFF
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RT9245A
EA Rising Slew Rate
PGOOD V(SS)
VFB
VOUT
OV
Figure 23. Waveform for OV
VCOMP
CH1:(500mV/Div) CH2:(2V/Div)
Error Amplifier Characteristic For fast response of converter to meet stringent output current transient response, RT9245A provides large slew rate capability and high gain-bandwidth performance.
Time (250ns/Div)
Figure 25. EA Falling Transient with 10pF Loading; Slew Rate = 8V/us
4.7k B 4.7k
EA +
A
EA Falling Slew Rate
VDAC
VFB
Figure 26. Gain-Bandwidth Measurement by signal A divided by signal B
VCOMP
CH1:(500mV/Div) CH2:(2V/Div)
Time (250ns/Div)
Figure 24. EA Rising Transient with 10pF Loading; Slew Rate = 8V/us
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RT9245A
0dB
180
Figure 27. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at 10.86MHz Design Procedure Suggestion a.Output filter pole and zero (Inductor, output capacitor value & ESR). b.Error amplifier compensation & sawtooth wave amplitude (compensation network). c.Kelvin sense for VCORE. Current Loop Setting a.GM amplifier S/H current (current sense component DCR, CSN pin external resistor value). b.Over-current protection trip point (RIMAX resistor). VRM Load Line Setting a.Droop amplitude (ADJ pin resistor). b.No load offset (RCSN2) c.DAC offset voltage setting (VOSS pin & compen- sation network resistor RB1). Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a.Kelvin sense for current sense GM amplifier input. b.Refer to layout guide for other items. Voltage Loop Setting Design Example Given : Apply for four phase converter VIN = 12V VCORE = 1.4V ILOAD = 30A to 125A VDROOP = 95mV with load (1m Load Line) OCP trip point set at 40A for each channel (S/H) DCR = 1m of inductor at 25C L = 0.3H COUT = 5600F with 1m equivalent ESR.
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DS9245A-05 March 2007
RT9245A
1. Compensation Setting a. Modulator Gain, Pole and Zero : From the following formula: Modulator Gain = VIN/VRAMP = 12/1.9 = 6.3 (i.e 16dB) where VRAMP : Ramp amplitude of saw-tooth wave LC Filter Pole = 3.88kHz and ESR Zero = 28kHz b. EA Compensation Network : Select RB1 = 1.5k, RB2 = 15k, C1 = 2.7nF, C2 = 5.6pF, C3 = 680pF and use the Type 3 compensation scheme shown in Figure 28. By calculation. 1 FZ1 = = 156kHz 2 x RB1 x C3 FZ2 = FP = 1 = 3.9kHz 2 x RB2 x C1 3. Over-Current Protection Setting Consider the temperature coef f icient of copper 3900ppm/C,
1 x VIMAX 1 x IL x DCR 3 R CSN 2 RIMAX 1 x 1V 1 x 40A x 1.39m 3 330 2 RIMAX
C3 680pF RB1 1.5k C2 5.6pF RB2 C1
15k 2.7nF EA +
Figure 28. Type 3 compensation network of EA The over all loop gain with load is shown in Figure 29 to Figure 31.
1 = 5.8kHz 2 x RB2 x (C2//C1)
RIMAX = 8.9k 4. Soft-Start Capacitor Selection For most application cases, 0.1F is a good engineering value.
Middle Band Gain = 10 (i.e. 20dB)
Figure 29. The Frequency Response with No Load
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RT9245A
Figure 30. The Frequency Response with Middle Load
Figure 31. The Frequency Response with Heavy Load
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DS9245A-05 March 2007
RT9245A
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path.
SW1
L1
VIN RIN CIN
VOUT
COUT
RL
V
SW2 L2
Figure 32. Power Stage Ripple Current Path
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RT9245A
+12V 0.1uF VCC BOOT UGATE PWM PHASE CIN LGATE PGND Locate near MOSFETs For Thermal Couple CSPx ADJ CBOOT LO1 Next to IC +12V or +5V PWM RT VOSS COMP CC RCSN CSN FB RFB SGND GND RT9245A RC Locate next to FB Pin VCC CBP Next to IC +5VIN
VCORE
COUT
RT9619
Figure 33. Layout Consideration
Figure 34. Layout of power stage
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DS9245A-05 March 2007
RT9245A
Outline Dimension
D L
E
E1
e
A A1 b
A2
Symbol A A1 A2 b D e E E1 L
Dimensions In Millimeters Min 0.850 0.050 0.800 0.178 9.601 0.650 6.300 4.293 0.450 6.500 4.496 0.762 Max 1.200 0.152 1.050 0.305 9.804
Dimensions In Inches Min 0.033 0.002 0.031 0.007 0.378 0.026 0.248 0.169 0.018 0.256 0.177 0.030 Max 0.047 0.006 0.041 0.012 0.386
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
DS9245A-05 March 2007
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